Signal delay in RC networks

A A DIWAN

Abstract


In this, paper, a new method tor approximating the step response of RC networks is presented. The method is useful in VLSJ design, where it is important to estimate the delay introduced by an interconnection network. The method computes an N exponent approximation to the step response by approximating the Laplace transform orthe response. An important future of this approach is that the computation time depends only on the topology of the network and is independent of the values of the resistances and capacitances in the network. this is very useful when approximating the step response of stiff networks. Another feature of this approach is that distributed RC lines can also be simulated. The convergence of the approximations to the actual response as N ->00 is easily shown by using Laplace transforms.

Keywords


RC networks; VLSI design; interconnection network; circuit simulation.

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