Design of fast pipelined arithmetic units in VLSI

Abstract

In this paper we propose a constant time pipelined adder and multiplier. Traditionally efficient carry-lookahead adders concentrate on making the design regular so that it can be laid out in VLSI. This paper looks at the construction of constant time adders that are regular and technology independent. However, the constant can be made larger or smaller and depends on the area used. The  absolute delay is stiB O(logn) and area used is O(n logn). Actual layout of a processor is shown in NMOS following the Mead and  Conway design rules.