Performance Limitations of Si Bulk CMOS and Alternatives for future ULSI

Abstract

Diminishing improvement in the on current (ION) and increase in off current (IOFF) may limit the scaling of bulk Si CMOS. There are several technical issues that make proper device scaling increasingly difficult. Various techniques like ultra-thin gate dielectrics, shallow source/drain junctions and high channel doping are used to mitigate the short channel effects and improve the device performance. Most of these approaches however directly conflict with the goal of obtaining high carrier mobility, low subthreshold swing, low series resistance, and therefore large ION and low IOFF at low supply voltage. To continue scaling beyond the 22 nm node, various architectural and material changes in the traditional MOSFET would be required for efficient operation of the transistor as a switch. A channel material with high mobility and therefore high injection  velocity can increase on current and reduce delay. Currently, strained-Si bulk CMOS is the dominant technology and increasing the strain provides a viable solution to scaling. However, looking into future scaling of nanoscale MOSFETs it becomes important to look at higher mobility materials, like Ge and III-V materials together with innovative device structures, like the multi-gate FETs (MuGFETs) with high- dielectrics, metal gate and Schottky source/drain. For both Ge and III-V devices problems of leakage need to be solved. Novel heterostructures will be needed to exploit the promised advantages of Ge and III-V based devices.