Nanoelectronics Era : Novel Device Technologies Enabling Systems on Chips

Abstract

The issues in scaling the Complementary Metal Oxide Semiconductor (CMOS) transistors in sub-100 nm regime are reviewed. The non-classical CMOS device technologies such as high-k gate dielectrics, strained silicon channel, Silicon On Insulator, multi-gate transistors, and metal gate electrodes, are discussed in detail. These techniques are expected to scale the CMOS devices to an ultimate limit of 5 nm physical gate length. The system level issues of growing power dissipation and increasing device to device variability in the chips should be overcome for the successful realization of complex systems in nanoelectronics technologies. A brief overview of the non-CMOS memory and logic device architecture is provided. The opportunities in building hybrid systems on chips by combining sensors and actuators along with the compute and storage functions on a single chip are described.